In recent years, for further improvement in the performance of semiconductor devices, research and development in layered semiconductor devices having substrates such as semiconductor substrates having a semiconductor device layer formed thereon or organic substrates piled up vertical to the surface of the plurality of substrates, is in progress in addition to refinement of transistors and wiring. As a layered semiconductor device, e.g. one having semiconductor substrates and organic substrates laminated is known, and more specifically, a three-dimensional layered semiconductor device having a structure such that semiconductor substrates are connected e.g. by electric signal terminals such as solder bumps, a space between the substrates is filled with an interlayer filler composition, and the substrates are bonded by the interlayer filler layer (for example, Patent Document 1).
Various problems of such a layered semiconductor device have been pointed out, and one of them is a problem of dissipation of heat generated from a device such as a transistor or wiring, and as one means to solve such a problem, an increase in the thermal conductivity of the interlayer filler composition may be mentioned. Specifically, the thermal conductivity of the interlayer filler composition is increased by using a highly thermally conductive epoxy resin as a thermosetting resin constituting an adhesive component of the interlayer filler composition or by using such a highly thermally conductive resin and a highly thermally conductive inorganic filler in combination. For example, an interlayer filler composition having as a filler spherical boron nitride agglomerates blended has been known (for example, Patent Document 2).
As a process for producing a layered semiconductor device having an interlayer filler composition filled in between substrates, a process by a pre-application method has been proposed in which a layer comprising an interlayer filler composition (Inter Chip Fill, hereinafter sometimes referred to as ICF) is formed, followed by heating as the case requires for B-stage formation, chips are cut out by dicing, a plurality of the obtained semiconductor substrates are laminated, temporary bonding by pressure heating is repeatedly carried out, and finally main bonding is carried out under pressure heating conditions (for example, Non-Patent Document 1).
Among such proposals of techniques such as a pre-application method for the purpose of practical use of a layered semiconductor device, a technique to improve the flowability (liquefaction) of an epoxy resin composition when a filler is densely filled in an ICF and to maintain the improved flowability (for example, Patent Document 3) and a technique to add a super engineering plastic for the purpose of improving the toughness of an epoxy resin composition have been proposed (for example, Non-Patent Document 2).